1. Field of the Invention
The present invention is related to a memory, and more particularly, to a memory with a disabling circuit for disabling the memory when the memory is defined as a NG (Not Good) part.
2. Description of the Prior Art
Semiconductor chips, for applications such as memory, have been made from wafers of semiconductor material whereby each wafer is split up into a plurality of dies. During the manufacture process, the wafer undergoes a number of micro-fabrications such as doping, etching, deposition of various materials and photolithographic patterning. Subsequently the wafer is then diced and further packaged.
Generally, wafer testing is performed before the wafer is sent to die preparation/packaging. The process of wafer testing in general can be referred to in several types such as Wafer Sort (WS), Wafer Final Test (WFT), Electronic Die Sort (EDS) and Circuit Probe (CP). During wafer testing all dies present on the wafer are tested by applying specific test patterns. If a die fails a certain test pattern, this particular die is classified as an NG part.
Wafer fabrication plants and test/package sites are of different vendors, or situated at different countries or locations. After the wafers are fabricated the wafer fabrication plants generally carry out a simple probe test to the wafers. The wafers are then sent to test/package sites for back-end processing (e.g. test and package). A wafer map is included to show the distribution of the NG parts and other relative data, so the test/package sites can skip the NG parts accordingly. However, it is still possible for the NG parts to be mistakenly packaged. Although the parameters of the final test is designed to be tighter than the probe test, the NG parts may still pass the final test due to issues such as testing hardware, testing environment, and test item variation. In addition, even if the NG parts are successfully filtered out by the final test, the NG parts have already been packaged into memory ICs (Integrated Circuits), affecting the yield, testing efficiency and the cost.